Looking at the figure alongside, we see some important configurations done around two 4017 ICs pin-outs. Let’s try to understand them in a step wise manner:
Pin #16 is the positive and pin #8 is the negative and are connected to their respective positions.
Pin #13 is also grounded; not following this would latch the output and stop its proceeding.
All the outputs as shown in the figure are terminated with LEDs, so that the shifting sequence may be visualized.
Pin #15 is the reset input and requires to be grounded and therefore is pulled to the grounded level via R1.
Interestingly a capacitor C1 is connected across the positive and the pin #15. When power is switched ON, instantaneously the voltage passes through this capacitor and reaches pin #15 to reset it. Resetting the IC makes it sure that the sequence begins from the first pin onwards which is #3 and not from any other intermediate pin-out.
Pin #14 which is the clock inputs of the ICs are permanently held at the positive supply level via R2 and R3. It means, now it will respond only to the falling edges of the input pulses or in simple words to the negative pulses.
You may build an oscillator circuit by using either IC 4049, 4060 or 4093, for driving the present circuit.
Now, when power is switched ON, as explained above the ICs are reset and their the sequence initiates from pin #3 which is the first pin of the sequence in response to the clock input at pin #14.
However, at this instant except pin #3 rest all other pin-outs are at logic low level and so is pin #11 of IC 2.
This simply means that at this instant the clock input pin #14 of IC1 is rendered inactive, because it is permanently held to ground via D3 and pin #11 of IC 2 and thus cannot respond to the input clocks.
But IC 2 is free to move and its outputs start shifting sequentially until it reaches its last pin #11 when it becomes high and releases pin #14 of IC1.
IC1 now initiates, but the moment the logic level from its pin #3 flips from high to low, pin #14 of IC2 this time is rendered inactive and is clamped via D4 and pin #3 of IC1.
In the meantime, IC1 continues its output’s sequential journey until again its pin #3 becomes high and the cycle is repeated.
The above configuration results in a continuous sequence of shifting logic high pulses from both the ICs in 18 steps. That’s exactly what we were looking for.