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Classification Of Machine Cycles

written by: shankar • edited by: KennethSleight • updated: 12/31/2009

The timing diagram of a microprocessor consists of machine cycles and instruction cycles. There are different types of machine cycles and they are based on various factors. Read here to know about the machine cycle and its types in detail.

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    Introduction

    A machine cycle is the time required to complete one operation of accessing the memory, I/O or acknowledge an external signal or request. Usually machine cycle consists of 3 to 6 T-states. In this article let us discuss about their different types and how they are being classified.

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    Types of machine cycle

    There are various types of machine cycles which are classified based on

    Status signals (IO/M’, S1 and S0)

    Control Signals (RD’, WR’, INTA)

    The different types of machine cycle available in 8085 microprocessor are:

    • Opcode Fetch
    • Memory Read
    • Memory write
    • I/O Read
    • I/O Write
    • INTR Acknowledge
    • Bus Idle

    Types of machine cycle  

    In this article let us discuss about the Opcode fetch machine cycle, memory read and I/O read machine cycles.

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    Opcode fetch machine cycle

    The Opcode fetch cycle, fetches the instructions from memory and delivers it to the instruction register of the microprocessor. For any instruction cycle, Opcode fetch is the first machine cycle. We know that each machine cycle may have 3 to 6 T-states. This Opcode fetch machine cycle consists of 4 T-states.

    T1 State:

    During the T1 state, the contents of the program counter are placed on the 16 bit address bus. The higher order 8 bits are transferred to address bus (A8-A15) and lower order 8 bits are transferred to multiplexed A/D (AD0-AD7) bus.

    After the address bits are transferred, the ALE (address latch enable) signal goes high. As soon as ALE goes high, the memory latches the AD0-AD7 bus. At the middle of the T state the ALE goes low and the complete 16-bit address is made available for the Opcode fetch machine cycle.

    T2 State:

    During the beginning of this state, the RD’ signal goes low to enable memory. It is during this state, the selected memory location is placed on D0-D7 of the Address/Data multiplexed bus.

    T3 State:

    In the previous state the Opcode is placed in D0-D7 of the A/D bus. In this state of the cycle, the Opcode of the A/D bus is transferred to the instruction register of the microprocessor. Now the RD’ goes high after this action and thus disables the memory from A/D bus.

    T4 State:

    In this state the Opcode which was fetched from the memory is decoded.

    Thus the cycle completes after 4 T-states. This very well explains the Opcode fetch machine cycle. For better understanding of the concept, a diagram explaining Opcode fetch cycle is shown below.

    opcode fetch machine cycle  

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    Memory Read machine cycle

    If the instruction is only one byte in length, then one machine cycle is enough to complete the process (Opcode fetch cycle). When the instruction has more than one byte of information to be processed, then the microprocessor may require more than one machine cycle to complete the process. The machine cycle in this case would require reading of address or data from memory or any other I/O devices. Hence these are known as memory read or I/O read machine cycles. These machine cycles have 3 T-states.

    A simple example for memory read machine cycle is MVI D, 24H

    For the above example there are 2 machine cycles involved. One is the Opcode fetch cycle and the second one is the memory read cycle which transfers the operand 24H from the memory to the microprocessor.

    T1 state:

    In this state the contents of the program counter is placed on the higher order address bus (A8-A15) and lower order address and data multiplexed (AD0-AD7) bus. ALE goes high so that the memory latches the (AD0-AD7) and then during the middle of the T1 state ALE goes low, so that complete 16-bit address are available.

    The microprocessor then identifies the memory read machine cycle from the status signals IO/M’=0, S1=1, S0=0. This condition indicates the memory read cycle.

    T2 state:

    Selected memory location is placed on the (D0-D7) of the A/D multiplexed bus.

    T3 State:

    The data which was loaded on the previous state is transferred to the microprocessor. In the middle of the T3 state RD’ goes high and disables the memory read operation. The data which was obtained from the memory is then decoded.

    The concept can be understood better with the aid of the diagram shown below.

    Memory read cycle  

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    I/O read machine cycle

    This machine cycle is very similar to memory read machine cycle. It is a 2 byte-I/O read instruction.

    A simple example is IN 22H.

    The first machine cycle is same as the memory read machine cycle, which is the Opcode fetch cycle. The second machine cycle is the I/O read machine cycle, where the content of port addresses (22H in this case) is transferred to the microprocessor.

    The status signal for the I/O read machine cycle is different. The status signal values are IO/M’=1, S1=1, S0=0.

    In the next article let us continue with the other 4 types of the machine cycle.

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    Image courtesy

    "Microprocessor and its applications" by Manoharan





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