Timing diagram of various signals
Address latch enable:
Address latch enable is an active high signal. (i.e.) the latch becomes enabled when the signal is high. It is activated during the beginning of T1 state of each machine cycle and it remains active in the T1state. But in case of bus idle machine cycle it is not activated.
Data Bus (D0-D7):
While dealing with data bus, two types of data flow are possible. The data can be transferred from memory to microprocessor and vice versa.
This process occurs during the T2 and T3 states.
There are 2 cycles. One is Read machine cycle and the other is write machine cycle. In read machine cycle, the data will appear during the later part of T2 state, while in Write machine cycle the data will appear on the beginning of T2 state.
But for reading a data from memory or I/O device, first we need to select the required device. After selecting the device, the required data to be read or written is taken from the selected location and placed on data bus. A certain amount of time is required to perform this action. This time is called “access time”. But for write cycle the access time is 0. This is because the data to be written is present on the registers of microprocessor and so it can put the data directly to data bus without any time delay.
Lower byte address (A0-A7):
The lower byte of address is available on the time multiplexed address/date bus during the T1 state of machine cycle, except the bus idle machine cycle.
Higher byte addresses (A8-A15):
The higher byte addresses (A8-A15) is available for T1, T2 and T3 states of each machine cycle, except the bus idle machine cycle.
IO/M’, S0, S1:
From the previous discussions about 8085 microprocessor, we very well know that IO/M’, S0, S1 are the status signals of the microprocessor. These status signals decide the type of machine cycle is to be executed. So they remain activated from the beginning T1 state of a particular machine cycle and remains till the end of that machine cycle.
RD’ and WR’:
These 2 signals RD’ and WR’ decides the direction of the data transfer.
RD’ is Active: When RD’ goes active, the data is transmitted from memory, I/O device or any other peripherals to the microprocessor.
WR’ is active: When WR’ goes active, the data is transmitted from microprocessor to the memory or any other peripheral devices.
Now there might be a question arising within your mind.
Can both the signals become active at same time? The answer for this question is NO. In 8085 microprocessor either RD’ goes high or WR’ goes high. Both cannot take place at same time.
The data transfer both RD’ and WR’ takes place during T2 and T3 states of machine cycle. So these signals are activated during the T2 and T3 states.
In the next article let us explore the various types of machine cycles that are used in timing diagram.
"Microprocessor and Its applications" by Manoharan