This type of flip-flop is very similar to the one we discussed in the basic circuit. But however a certain difference exists. In this flip-flop circuit an additional control input is applied. This additional control input determines the when the state of the circuit is to be changed. This additional input is nothing but the clock pulse.
The RS flip-flop consists of basic flip-flop circuit along with two additional NAND gates and a clock pulse generator. The clock pulse acts as an enable signal for the two inputs. The output of the gates 3 and 4 remains at logic “1" until the clock pulse input is at 0.This is nothing but the quiescent condition of the flip-flop. Now let us see how it works.
Information from S and R is allowed to reach the output only when clock pulse goes to 1.
Let’s assume S=1, R=0 and CP=1. The set state is reached at this condition and since the clock pulse is 1, information from S and R is allowed to reach output.
From the truth table of NAND gate we can say that the output is 0 only when both the inputs are 1. In all the other case the output is 1.
So when S=1, R=0 &CP=1. Both the inputs to the gate 3 are 1 and hence its output is 0. This information (i.e.) 0 is passed to gate 1. Since one of the inputs of gate 1 is 0, we can say that the output Q=1. Since R=0, the output obtained at Q’=0.
Conclusion: When S=1, R=0 & CP=1 => Q=1 and Q’=0.
Now to change to reset state, the inputs must be S=0, R=1 & CP=1. The observed outputs are Q=0 & Q’=1.When the clock pulse returns to zero, the circuit remains in its previous state. This is applicable to both Set and Clear states.
Now when CP=1, inputs S=0 &R=0, that is when both the inputs are 0, the state of the circuit does not change.
When CP=1, S=1 & R=1, an indeterminate condition occurs. Because both the outputs Q and Q’ remain at 1. This is not possible because both the outputs are complementary to each other. So it is better to avoid this condition during practise.
These results can be compared with those in characteristic table; Where S and R are inputs. Q is the output and Q (t+1) shows the next state. The characteristic table should be interpreted as: for the given present state Q, the inputs S and R, the application of a single clock pulse CP causes the flip-flop to go to the next state. So CP is not indicated in the characteristic table.
The characteristic equation shows the value of the next state as a function of inputs and the present state. In the characteristic equation, the indeterminate states are marked as don’t cares in the map.