- slide 1 of 3
Although the function of a CMOS inverter or a NOT gate is pretty basic, it succeeds as one of the important members of the CMOS family. It finds wide and useful applications in many electronic circuits such as a noise suppressors and oscillators.
From the name itself it is obvious that its function is to invert a logic signal, i.e. if a logic '1' is applied to its input, a logic '0' will appear at its output and vice versa. CMOS inverter gates may be also used as buffers to reduce the load dependence of a circuit. These are the two most basic applications of this gate, but can be suitably modified in several ways to perform much complicated functions.
We will try to understand the suppressor design and oscillator design using simple circuit schematics.
- slide 2 of 3
As an Oscillator
Assuming initially the input N2 as logic'1' and consequently its output as logic'0', capacitor C immediately starts charging through R. It also keeps the input of N1 to logic'0' till the capacitor is fully charged. Now C can no longer hold the input of N1 to logic'0' and it toggles back to logic'1', N2 also changes state so that C starts discharging through R, when it is fully discharged the circuit returns back to its original position to repeat itself and the circuit starts oscillating. The oscillating frequency will depend on the values of R and C.
To learn more about the typical applications of the above discussed oscillator circuit, please connect to the following links:
Applications and characteristics of NOT gates or CMOS inverters are comprehensively discussed HERE. A must read.
- slide 3 of 3
It becomes highly undesirable to have a digital output that is superimposed by glitches. These are extremely short in the range of nanoseconds (ns) unstable sharp pulses which inevitably finds a place in almost every digital circuit.
CMOS inverter gates can be effectively used to cancel out these glitches. Referring to the figure, IC 4060 is wired as a square wave generator to produce output pulses at pin 15. Its frequency will depend on the values of R and C. These output pulses should be free from the glitches trying to make its way from the input of N1 to pin 12 of the IC. Assume that the circuit can suppress a glitch which is under 70ns. Initially as long as the out put of N6 is logic '0' the IC cannot react to any pulses, because its pin 11 is also at logic '1'. When a pulse (actual data) appears at the input of N1, it resets pin 12 of IC 4060 after 10ns( time taken to pass through N1).
N2...N5 with the capacitors together C1.....C4 produce a delay of say 70ns, so the signal reaches the output of N5 after a total delay of 80ns logic '0'. Thus pin 11 of the IC 4060 is no longer at logic high, enabling it to react to the input signal.
Any signal shorter than 70ns (glitch) will never reach the output of N6, and IC 4060 will be rendered inactive for these pulses. Therefore only actual data which are above 70ns are allowed to pass.